Full name: BAZYLEVYCH, Roman Petrovych


Title: Full Professor, Ph.D., D.Sc,

Software Department, Lviv Polytechnic National University


Address: 12 S.Bandery Str., Lviv, 79013, Ukraine

Tel: +38032 2582578 (work); +380322 765712 (home)

E-mail: rbaz@polynet.lviv.ua

Roman P. Bazylevych received the Ph.D. degree in electrical engineering from the Lviv Polytechnic Institute, and the Doctor of Engineering Sciences degree in computer sciences from the Leningrad Electrotechnic Institute. Currently he is working as Full Professor at Software Engineering Department of Lviv Polytechnic National University. He is a full member of the Shevchenko Scientific Society, Academician at Ukrainian Academy of Engineering Sciences, fellow member of the IEE, senior member of the ACM. R.Bazylevych conducted research at the Physical-Mechanical Institute of Academy of science of Ukraine, at Lviv Polytechnic National University, at University of California at San Diego and Harvard University.


Research Interest:

Computer Sciences, Combinatorial optimization, NP-hard problems, design automation, traveling salesman problem, partitioning, packaging, placement, routing.


Number of scientific publications: 380, including 5 scientific monographs, 2 textbooks, 11 patents


Supervisor of 14 Ph.D. and D.Sc. dissertations


Research projects: Scientific Leader of 72 research projects  (Grants and Contracts)


Selected articles for download:

 
1.Download R.P. Bazylevych, M. Palasinski et al. “Efficient decomposition algorithms for solving large-scale TSP”. In book: Computational models for business and engineering domain. ITHEA. Rzeszow-Sofia, 2014, Editors: Galina Setlak, Krassimir Markov. pp. 225 – 234.
2.Download R.P. Bazylevych, M. Palasinski et al. “Partitioning Optimization by Iterative Reassignment of the Hierarchically Built Clusters with Border Elements”. ÌÅÑÎ 2013. 2nd Mediterian Conference on Embedded Computing. 15-20 June, 2013, Budva, pp. 219 - 221.
3.Download R.P. Bazylevych, M. Palasinski et al. “Decomposition methods for large-scale TSP”. In book: G. Setlak, M. Alexandrow, K. Markow. “Artificial intelligence methods and techniques for business and engineering application”. ITHEA, Rzeszow –Sofia, 2012, pp. 148 – 157.
4.Download R.P. Bazylevych, M. Palasinski et al. “Macromodeling for VLSI physical design automation problems”. In book: Galina Setlak, Krassimir Markov. “Business and engineering applicatios of intelligent and information systems”. ITHEA, Rzeszow-Sofia, 2011, pp. 178 – 188.
5.Download R.P. Bazylevych, R. Dupas et al. A Parallel Approach for Solving a Large-Scale Traveling Salesman Problem. Proceedings of the Fifth Indian International Conference on Artificial Intelligence (IICAI-11), Tumkur, India, 2011, pp. 566 - 579.
6.Download R.P. Bazylevych, R.K. Kutelmakh et al. A Decomposition Algorithm for Uniform Traveling Salesman Problem. Proceedings of 4th Indian International Conference on Artificial Intelligence (IICAI-09), pp. 47-56.
7.Download R.P. Bazylevych, R. Kutelmakh et al. Decomposition and scanning optimization algorithms for TSP. Proceedings of the International Conference on Theoretical and Mathematical Foundations of Computer Science. – Orlando, USA. – 2008. – pp. 110-116.
8.Download R.P. Roman Bazylevych, Roman Kutelmakh, R'emy Dupas, Lubov Bazylevych. Decomposition algorithms for large-scale clustered TSP. 3-rd Indian Intern. Conf. on Artificial Intelligence (IICAI-07), Pune, India, 2007, pp. 255 – 267.
9.Download R.P. Roman Bazylevych, Ihor Podolskyy. “Partitioning optimization by trcursive moves of hierarchically built clusters”. Proc. Of 2007 IEEE Workshop on design and Diagnostics of electronic Circuits and systems. April 11 -23, 2007, Krakow, pp. 235 -238.
10.Download R.P. Bazylevych. The Optimal Circuit Reduction Method as an Effective Tool to Solve Large and Very Large Size Intractable Combinatorial VLSI Physical Design Problems. Proc. of 10-th NASA Symposium on VLSI Design, Albuquerque, March 2002, pp. 6.1.1 – 6.1.14.
11.Download R.P. Bazylevych, R.A.Melnyk, O.H.Rybak. Circuit partitioning for FPGAs by the Circuit Reduction Method. VLSI Design, Special Issue, Vol.11, No. 3, 2000, pp.237-248.
12.Download R.P. Bazylevych, T.M. Telyuk. VLSI and PCB elements placement optimizing using hierarchical scanning area method. Proc. 42 Int. Wissenschaftliches Kolloquium, Ilmenau, 1997, pp.594-599.



Ph.D. DISSERTATIONS SUPERVISED BY Dr. R.Bazylevych


1.Mathematical methods and software for solving Large Scale Traveling Salesman Problem. R.K. Kutelmakh.
2.Algorithms and software for placement of various size elements of electronic devices by combined methods of hierarchical optimization. I.F. Shcherb'yuk.
3.Hierarchical macromodeling in VLSI design. R.Melnyk.
4.Numerical and symbolic methods and algorithms for integrated circuits simulation. Ye.N. Fedorchuk.
5.Mathematical and software tools for elements placement by scanning area method. T.M. Teliuk.
6.Electronic elements placement by the method of multilevel decomposition and macromodelling and its realization for CAD Systems. N.P.Nikolov.
7.Algorithmic methods for analysis and optimization of active and digital filters transfer functions. R.A. Melnyk.
8.Computer simulation methods of radio devices with distributed RC-strucutres. Yu. M. Romanyshyn.
9.The development and investigation of methods for symmetrical HF Devices analysis and their realization for CAD Systems. R.Kharke
10.The development of methods for planar topology synthesis for special electronic devices and their realization for CAD Systems. E.V.Kharke.
11.The development and investigation of partitioning algorithms for Physical Design Automation. S.P.Tkachenko.
12.Optimization of circuit layout algorithms for Physical Design Automation. R.Pelke.
13.Software system for automatic design of electrical circuits with distributed RC elements. I.I.Motyka.
14.Symbolic algorithms for determination of circuit functions for linear circuits. R.V.Dmytryshyn.


SELECTED RESEARCH PROJECTS LEADED BY Dr. R.Bazylevych


1.Methodology and hybrid algorithms for solving large-scale intractable combinatorial problems. 2013-2014.
2.VLSI floor space minimization. 2009-2010.
3.Large-Scale Transportation and Network Problems with Specific Properties: Clustering and Evolutionary Approaches. 2007-2008.
4.Evolutional and Decomposition Algorithms for Dynamic Vehicle Routing Problem. 2005-2006.
5.Hierarchical clustering and macromodelling as an efficient and effective tools to solve large and very large size intractable combinatorial problems.2002-2003.
6.High efficient decomposition software (algorithms and programs) for high size intractable combinatorial problems. 2000-2001.
7.High performance software for VLSI and PCB Physical CAD, 1998 - 1999.
8.Computer localization, 1995.
9.Ukrainian language computer educating system, 1994-1995.
10.Mathematical methods and algorithms for solving large-scale combinatorial problems, 1994- 1995.
11.Mathematical and software tools for VLSI topology intelligence CAD systems, 1991 - 1993.
12.Decomposition CAD for VLSI, 1991.
13.Software development for hierarchical VLSI CAD, 1990.
14.Application of decomposition methods in CAD, 1989.
15.Software package improvement for placement and routing of IC, 1987 - 1988.
16.Decomposition methods and software development for VLSI CAD, 1986.
17.Algorithmic and package program development for one-level chip topology CAD, 1986.
18.Algorithmic and package programs development for partitioning, 1986.
19.Theoretical and applied problems of mathematical methods and CAD employment, 1986.
20.Program package development for routing PCB device, 1986.
21.Algorithm and program packages for physical CAD for radio-electronic devices, 1983.
22.Programs package for high frequency devices CAD, 1983.
23.Method's investigation and programs package development for TV high frequency integrated circuit CAD, 1982.
24.Computer design of high frequency integrated circuits, 1980.
25.Development of algorithms and program packages for CAD of radio-electronic devices, 1980.
26.Structure design for computer simulation of electrical circuitous system, 1978.
27.CAD operation system development, 1978.
28.Software development for packaging with standard cell covering and routing printed circuit boards with nonregular structure, 1977 - 1978.
29.Algorithm and software development for optimizing TV circuits, 1977.
30.Design of hybrid integrated circuit Physical CAD, 1977.
31.High frequency integrated circuit CAD, 1977.
32.Expansion of software package for routing of two-level printed circuit boards with nonregular pin placement, 1976.
33.Issue on radio-electronic devices CAD, 1975 - 1977.
34.Software development for routing of two-level printed circuit boards with nonregular pin placement, 1975.
35.Investigation and software development of computer analysis of TV devices, 1975.
36.Development of new methods of design and production of radio-electronic devices on the base of optimal quality parameters, 1974.
37.Software development for automatic design of linear high frequency circuits, 1973 -1974.
38.Linear circuits TV analysis, 1973.
39.Computer aided design of radio-electronic devices, 1971-1973.


SELECTED PUBLICATIONS


 Scientific books:
1.R.P.Bazylevych. Decomposition and Topological Methods for Physical Design Automation of Electronic Devices. Lviv: Vyshcha Shkola, 1981, 168 P., (In Russian).
2.R.P.Bazylevych. The Methods of Planar Topology Layout Synthesis of Electronic Devices. Lviv: Lviv Polytechnic Institute, 1986, 64 P. (In Russian).
3.R.P.Bazylevych. Algorithmic Methods of Flexible Routing. Kyiv: Institute of Cybernetics, Ukrainian Academy of Sciences, 1979, 52 P. (In Russian).
4.R.P.Bazylevych. Some problems of radio electronic devices planar topology synthesis. Kyiv, 1978, UkrNII, #1219, 101 P. (In Russian).
5.R.P.Bazylevych. Nonlinear Nonreactive Circuits. Kyiv: Naukova Dumka, 1967, 116 P., (In Ukrainian).
  Selected articles in scientific journals:
1.R. Bazylevych, R. Kutelmakh, B. Kuz’. Methods of input area clustering for TSP with constraints // Visnyk of Lviv National Polytechnic University. – 2010. – ¹ 672 : Computer sciences and information technologies. – P. 87-90 (In Ukrainian).
2.R. Bazylevych, R. Kutelmakh. Local Optimization Algorithm for the TSP // Radioelectronic and computer systems. – Kharkiv. – 2009. – ¹ 7(41). – P. 41-45 (In Ukrainian).
3.R. Bazylevych, R. Kutelmakh. Subset Joining Algorithm for Traveling Salesman Problem // Visnyk of Lviv National Polytechnic University. – 2009. – ¹ 653 : Information systems and networks. – P. 3-12 (In Ukrainian).
4.R. Bazylevych, R. Kutelmakh. Investigating the effectiveness of the existing methods for solving TSP // Visnyk of Lviv National Polytechnic University. – 2009. – ¹ 650 : Computer sciences and information technologies. – P. 235-245 (In Ukrainian).
5.R. Bazylevych, R. Kutelmakh. TSP solution optimization by the route scanning method // Visnyk of Lviv National Polytechnic University. – 2009. – ¹ 638 : Computer sciences and information technologies. – P. 254-260 (In Ukrainian).
6.R. Bazylevych, R. Kutelmakh. Decomposition algorithms for solving Traveling Salesman Problem // Visnyk of Lviv National Polytechnic University. – 2007. – ¹ 598 : Computer sciences and information technologies. – P. 138-148 (In Ukrainian).
7.R. Bazylevych, R. Dupas, R. Kutelmakh. Local optimization algorithms using for solving clustered TSP // Visnyk of Lviv National Polytechnic University. – 2006. – ¹ 565 : Computer sciences and information technologies. – P. 207-212 (In Ukrainian).
8.R. Bazylevych, R. Kutelmakh. Algorithms for dynamic creating of the working field for clustered TSP // Visnyk of Lviv National Polytechnic University. – 2006. – ¹ 565 : Computer sciences and information technologies. – P. 200-207 (In Ukrainian).
9.R.P.Bazylevych. The efficiency of cluster transition in decomposition problems. “Visnyk” of the Lviv Polytechnic National University, 2001, (In Ukrainian).
10.R.P.Bazylevych, I.Scherbiuk. Initial placement by the grouping and twolevel macromodeling. “Visnyk” of the Lviv Polytechnic National University, 2001, (In Ukrainian).
11.R.P.Bazylevych, R.A.Melnyk, O.H.Rybak. Circuit partitioning for FPGAs by the Circuit Reduction Method. VLSI Design, Special Issue, Vol.11, No. 3, 2000, pp.237-248.
12.R.P.Bazylevych, T.Teliuk, Elements on chip placement optimization. Contemporary computing in Ukraine, 2000 (In Ukrainian).
13.R.P.Bazylevych, M.Rachynskyi, Linear And Circular Placement By Multilevel Decomposition And Scanning Area Methods, Contemporary computing in Ukraine, 2000 (In Ukrainian).
14.R.P.Bazylevych, Hierarchical clasterization, decomposition and multilevel macromodelling – the effective and efficient tools to solve the high and very high size combinatorial circuit type problems. Contemporary computing in Ukraine, 2000 (In Ukrainian).
15.R.P.Bazylevych, I.Scherbiuk. The placement elements optimization by the scanning area method. Computers printing technologies. Ukrainian Printing Academy, Lviv, 2000, (In Ukrainian).
16.R.P.Bazylevych, M.Rachynskyi. The improvement of effectiveness of the scanning area method. Computers printing technologies. Ukrainian Printing Academy, Lviv, 2000, (In Ukrainian).
17.R.P.Bazylevych. The partitioning of the large circuits by the optimal circuit reduction method. Computers printing technologies. Ukrainian Printing Academy, Lviv, 2000, (In Ukrainian).
18.R.P.Bazylevych, R.A.Melnyk, O.G.Rubak. Circuit partitioning by the optimal circuit reduction method. VLSI Design, . Vol 11, No 3, 2000.
19.R.P.Bazylevych, O.H.Rybak. The optimization of VLSI packaging by the optimal circuit reduction method. Visnyk Lviv Polytechnic State University, 385, 1999.
20.R.P.Bazylevych, O.H.Rybak. The initial VLSI packaging by the optimal circuit reduction method. Visnyk Lviv Polytechnic State University, 385, 1999.
21.R.P.Bazylevych, T.M.Telyuk. Some possibilities of increasing quality of element placement by the scanning area method on the basis of sthohastic algorithms. Visnyk Lviv Polytechnic State University `The Computer Engineering and Information’s Technologies`, # 370, 1999, pp.148-153 (In Ukrainian).
22.R.P.Bazylevych, T.M.Telyuk, I.V.Podolskyi, T.I.Demianetch, R.P.Stupinskyi. The investigation of topology LSI circuit element placement. Visnyk Lviv Polytechnic State University `The Computer Engineering and Information’s Technologies`, # 370, 1999, pp.86-90 (In Ukrainian).
23.R.P.Bazylevych, O.H.Rybak. The top-down algorithm for dividing the circuits into several partitions Visnyk Lviv Polytechnic State University `The Computer Engineering and Information’s Technologies`, # 349, 1998, pp.181-185, 1998 (In Ukrainian).
24.R.P.Bazylevych, T.M.Telyuk, Horlata M.M., Hladshteyn A.Ya., Rybak O.H. The investigation of partitioning parameters influence for placement element's performance by the method of hierarchical decomposition. Visnyk Lviv Polytechnic State University `The Computer Engineering and Information’s Technologies`, # 351, 1998, pp.136-141 (In Ukrainian).
25.R.P.Bazylevych, O.H.Rybak. The driven dichotomy algorithms with given initial conditions. Visnyk Lviv Polytechnic State University `The Computer Engineering and Information’s Technologies`, # 349, 1998, pp.185-191, 1998 (In Ukrainian).
26.R.Bazylevych, O.Rybak. The algorithm for initial packaging by optimal circuit reduction method. Computers printing technologies. Ukrainian Printing Academy, Lviv, 1998, -pp.46-47 In Ukrainian).
27.R.Bazylevych, O.Rybak. The algorithm for packaging optimization by optimal circuit reduction. Computers printing technologies. Ukrainian Printing Academy, Lviv, 1998, -pp.40-41(In Ukrainian)
28.R.P.Bazylevych, T.M.Telyuk. Multilevel hierarchical scanning area method. Visnyk Lviv Polytechnic State University `The Computer Engineering and Information’s Technologies`, 1997, -N 322. - pp.3 -6.
29.R.P.Bazylevych, T.M.Telyuk. Utilization of mutation as a genetic algorithm's procedure for VLSI placement in scanning area method. Visnyk Lviv Polytechnic State University `The Computer Engineering and Information’s Technologies`, 1996, -N 307. - pp. 3 -6.
30.R.P.Bazylevych, T.M.Telyuk. The basic decomposition procedure for scanning area. Visnyk of Lviv Polytechnic State University, 1995, -N 294. - pp.5 - 10.
31.R.P.Bazylevych. Computerization and Ukrainian language. The News of Ukrainian engineers. N.Y., N 1/3, 1993 (In Ukrainian).
32.R.P.Bazylevych, O.M.Kossak. Informatics in Ukraine. The News of Ukrainian engineers. N.Y., N 3-4, 1992 (In Ukrainian).
33.R.P.Bazylevych, N.Nikolov. The Application of the Scanning Area Method for Infinite Space. Elektrotekhnika i Elektronika. N 5-6, 1991, Sofia, p.13-14 (In Bulgarian).
34.R.P.Bazylevych, R.A.Melnyk, A.Huc. Matrix LSI placement by partitioning algorithms. Vestnik Lvovskoho politekhnicheskoho instituta, N 226, 'Teoriia i proektirovanie poluprovodnikovykh i radioelektronnykh ustroistv', Lviv, 1988, pp.99-100 (In Russian).
35.R.P.Bazylevych, R.A.Melnyk. LSI placement by macromodeling. Avtomatizaciya tekhnicheskoho proektirovania REA i EVA. Penza, 1986, pp.67-68 (In Russian).
36.R.P.Bazylevych, N.P.Nikolov. The macromodels for multilevel placement. Avtomatizaciya tekhnicheskoho proektirovania cifrovoi apparatury. Kaunas, 1984, pp.57-58 (In Russian).
37.R.P.Bazylevych, M.R.Pankiv. The investigation of scanning area method. Izvestiia VUZ'ov SSSR, Radioelektronika, v.26, N 6, 1983, pp.64-67 (In Russian).
38.R.P.Bazylevych. Investigation of parallel reduction method for partitioning problems. Vychislitelnaia tekhnika, Kaunas, 1981, pp.90-92 (In Russian).
39.R.P.Bazylevych. Some planar topology problems with considering physical design constraints. Matematicheskoe, programnoe, informacionnoe i tekhnicheskoe obespechenie sistem avtomatizacii proektirovania. Saratov, 1982, pp.32-35 (In Russian).
40.R.P.Bazylevych. Planar topology layout synthesis with invariant contacts on two-line or two-cycle structure. Avtomatizaciia konstruktorskoho proektirovaniia radioelektronnoi i elektronno-vychislitelnoi apparatury. Saratow, 1981, pp.70-71 (In Russian).
41.R.P.Bazylevych. Macromodeling for elements placement problem. Elektronnoe modelirovanie, N 3, 1981, pp.87-93 (In Russian).
42.R.P.Bazylevych, M.R.Pankiv. Placement optimization by scanning area method. Vestnik Lvovskoho politekhnicheskoho instituta, N 152, Lviv, 1981, pp.7-10 (In Russian).
43.R.P.Bazylevych, O.Z.Yasenyckii, R.T.Panchak. Local optimization algorithms for the flexible routing method. Vestnik Lvovskoho politekhnicheskoho instituta, N 142, Lviv, 1980, pp.42-46 (In Russian).
44.R.P.Bazylevych. Some planar topology synthesis problems. Vychislitelnaia tekhnika, V. 12, Vilnius, 1979, pp.16-23 (In Russian).
45.R.P.Bazylevych. The partitioning control for the parallel reduction method. Vestnik Lvovskoho politekhnicheskoho instituta. N 134, Lviv, 1979, pp.55-60 (In Russian).
46.R.P.Bazylevych. The planar topology synthesis for two-line contact structure. Izvestiia VUZ'ov-Radioelektronika, N 9, 1979,pp.87-89 (In Russian).
47.R.P.Bazylevych, I.V.Parkanii, S.B.Ernst. Algorithms for nonregular routing. Vychislitelnaia tekhnika N 12, Vilnius, 1979, pp.29-32 (In Russian).
48.R.P.Bazylevych. Decomposition utilization for solving placement problem. Vestnik Lvovskoho politekhnicheskoho instituta, N 136, Lviv, 1979, pp.43-46 In Russian).
49.R.P.Bazylevych. Approximate methods for planar topology layout synthesis of computer units. Mashinnye metody proektirovania elektronno-ychislitelnoi apparatury. Leningrad, 1979, pp.42-46 (In Russian).
50.R.P.Bazylevych, O.Z.Yasenyckyi. The topology route models in flexible routing method. Izvestiia VUZ'ov-Radioelektronika, N 11, 1978, pp.74-79 (In Russian).
51.R.P.Bazylevych. The basic principles and generalization of flexible connection routing. Upravliaiushchie sistemy i mashiny. N 6, 1977, pp. 103-112 (In Russian).
52.R.P.Bazylevych, O.Z.Yasenyckyi. The complex models of flexible routes. Vychislitelnaya tekhnika."Avtomatizirovannoie tekhnicheskoie proektirovanie cifrovykh vychislitelnykh mashyn.” Kaunas, 1977, pp.111-114 (In Russian).
53.R.P.Bazylevych, Yu.M.Romanyshyn. The radioelectronic circuit analysis by optimal subcircuit reduction method. Izvestiia VUZ'ov-Radioelectronika, N 6, 1977, pp.52-56 (In Russian).
54.R.P.Bazylevych, R.Pelke. The ordering algorithms for routing at analog routing area model. Vychislitelnaia tekhnika, V.8, Kaunas, 1976, 120-123 (In Russian).
55.R.P.Bazylevych, O.Z.Yasenyckyi. Flexible multilevel regular PCB routing. Vychislitelnaia tekhnika, V.8, Kaunas, 1976, 124-127 (In Russian).
56.R.P.Bazylevych, S.P.Tkachenko. Solving the problem for partitioning with the method of parallel reduction. Vychislitelnaya Tekhnika, Kaunasskiy olitekhnicheskiy Institut, Kaunas, 1975, p.295-298 (In Russian).
57R.P.Bazylevych, N.F.Storozenko. The algorithm for formation full planar graph. Visnyk Lvivskoho Politekhnichnoho Instytutu, N 88, 1974, pp.94-97 (In Ukrainian).
58.R.P.Bazylevych. General approach for computer planar routing. Izvestiia VUZ'ov SSSR-Radioelektronika, N 6, 1974, pp.98-103 (In Russian).
59.R.P.Bazylevych, E.F.Zamora, N.F.Storozenko. The flexible routing algorithm for PCB. Visnyk Lvivskoho Politekhnichnoho Instytutu, N 76, 1973, p.83-88 (In Ukrainian).
 Selected articles in Conference Proceedings:
1.R. Bazylevych, M. Palasinski et al. Decomposition Methods for Large-Scale TSP. 5th International Conference on Intelligent Information and Engineering Systems INFOS 2012, Rzeszow – Krynica-Zdroj, Poland, 2012.
2.R. Bazylevych, R. Dupas et al. A Parallel Approach for Solving a Large-Scale Traveling Salesman Problem. Proceedings of the Fifth Indian International Conference on Artificial Intelligence (IICAI-11), Tumkur, India, 2011.
3.R. Bazylevych., R. Kutelmakh et al. A Decomposition Algorithm for Uniform Traveling Salesman Problem. Proceedings of 4th Indian International Conference on Artificial Intelligence (IICAI-09), Tumkur, India, 2009.
4.R. Bazylevych., R. Kutelmakh et al. Parallel approach for solving large-scale clustering TSP. Proc. of 10 Intern.Conf. “The experience of designing and application of CAD system in microelectronics”, CADSM-2009, Poliana, Svaliava, 28 – 29 Febr., 2009.
5.R. Bazylevych. Large and very large-scale placement. Proc. IEEE East-West Design and Test Symposium. Moscow, Sept. 18-21, 2009, pp. 179 –182.
6.R. Bazylevych., R. Kutelmakh et al. Decomposition and scanning optimization algorithms for TSP. Proc. Intern. Conf. on Theoretical and Mathematical Foundation of Computer Science. July 7-10, Orlando, USA, 2008.
7.R. Bazylevych., R. Kutelmakh et al. Decomposition algorithms for large-scale clustered TSP. 3-rd Indian Intern. Conf. on Artificial Intelligence (IICAI-07), Pune, India, 2007.
8.R. Bazylevych. Investigation of optimization by Optimal Circuit reduction method. Proc. IEEE of EWDT, Krakow, 2007.
9.R. Bazylevych., R.K. Kutelmakh et al. Decomposition of clustered TSP. Ñonference scientifique conjointe en Recherche Operationnelle et Aide a la Decision, FRANCORO V/ ROADEF 2007, Livre des resumes, Grenoble, France, 2007.
10.R.P.Bazylevych. Optimal Circuit Reduction Method as an Effective Tool for Large-Scale Combinatorial Nonpolinomial Problems Solving for Physical Design Automation of VLSI. Proceedings of Russian Conference “Problems of developing microelectronics system – 2005”, Institute of Design Problems in microelectronics of Russian Academy of Science, Moscow, October, 2005.
11.R.Bazylevych. The Optimal Circuit Reduction Method as an Effective Tool to Solve Large and Very Large Size Intractable Combinatorial VLSI Physical Design Problems. Proc. of 10-th NASA Symposium on VLSI Design, Albuquerque, March 2002.
12.R.Bazylevych, P.Bazylevych. Solving of nonpolinomial combinatorial high size problem. The implementation of information technologies in economy and business. State tax academy of Ukraine. Kyiv, 2000.
13.R.Bazylevych, O.Rybak. Packaging algorithms on the base of the optimal circuit reduction method. 44 Int. Wissenschaftliches Kolloquium, Ilmenau, 1999.
14.R.P.Bazylevych, T.M.Telyuk. VLSI and PCB elements placement optimizing using scanning area inside scanning area method, Int. Conf. on Genetic Algorithms “Mendel-97”, Brno, June, 1997.
15.R.P.Bazylevych, T.M. Telyuk. VLSI and PCB elements placement optimizing using hierarchical scanning area method. Proc. 42 Int. Wissenschaftliches Kolloquium, Ilmenau, 1997, pp.594-599.
16.R.P.Bazylevych, T.Telyuk. Some possibilities of genetic algorithms application for physical design of electronic devices. Int. Conf. for Genetic Algorithms, Odessa, 1995, p.217.
17.R.P.Bazylevych, T.Telyuk. Application of mutants as operators of genetic algorithms for optimizing VLSI and PCB element placement on the basis of the scanning area method. Proc.Int.Conf. on Genetic Algorithms "Mendel-95", Brno, 1995, p.25-27.
18.R.P.Bazylevych, Yu.Rakhleckyi. Program package for decomposition investigation. Proc.Int.Conf. "Ukrsoft-94,” Lviv, 1994, p.3. (In Ukrainian).
19.R.P.Bazylevych, T.Telyuk. Software Based on Scanning Area Method for Element Placement Optimization. Proc.Int.Conf. "Ukrsoft-94,” Lviv, 1994, p.22-26 (In Ukrainian).
20.R.P.Bazylevych, T.Telyuk. High speed base operators in the scanning area method. Proc.Int.Conf."Ukrsoft-93", Lviv, 1993, p.80-81 (In Ukrainian).
21.R.P.Bazylevych, V.M.Semotiuk, O.I.Felyshtyn. Project UKRSCII for Ukrainian alphabet coding. Proc.Conf."Ukrsoft-93", 1994, pp.16-18 (in Ukrainian).
22.R.P.Bazylevych, R.A.Melnyk. Adaptive system for VLSI circuits layout design. Proc.Lith.Conf. of Radioelectronics, Kaunas, 1991, p.91-92 (In Russian).
23.R.P.Bazylevych, R.A.Melnyk, S.V.Tykailo. Decomposition algorithm for various size element placement. Proc.Conf.Conf."Avtomatizacia proektirovania REA i EVA", Penza, 1990, pp.58-60 (In Russian).
24.R.P.Bazylevych, Medynskyi, S.V.Tykailo. Arbitrarily sized elements placement algorithm. Proc.Conf."Proektirovanie sredstv vychislitelnoy tekhniki.” Kaunas, 1989, pp.205-206 (In Russian).
25.R.P.Bazylevych, R.A.Melnyk. Routing for Matrix LSI. Proc.Conf. "1st Intern. Conf.SAPR SVT-89" .S.3, Moscow, 1989, pp.108-110 (In Russian).
26.R.P.Bazylevych, R.A.Melnyk, V.A.Yarnykh, S.V.Tykayilo, N.E.Shpak. VLSI topology Computer-Aided Design. Proc.Conf. "1st. Intern. Conf. SAPR SVT-89", S.3, Moscow, 1989, pp.55-58 (In Russian).
27.R.P.Bazylevych, R.A.Melnyk, C.V.Tykaylo. The Computer-Aided Design of VLSI layouts. Proc Conf. " 1st Int.Conf.SAPR SVT-89,” Moscow. 1989, p.55-58 (In Russian).
28.R.P.Bazylevych, R.A.Melnyk. The placement problem in CAD Matrix LSI system. Proc.Conf. "Mashinnye metody proektirovania elektronno-vychislitelnoi apparatury,” Kaunas, 1988, pp.20-21 (In Russian).
29.R.P.Bazylevych, R.A.Melnyk, M.R.Pankiv. The software for partitioning. Proc.Conf. "Teoriia i praktika postroeniya intelektualnykh sistem avtomatizirovannoho proektirovania REA i BIS". Moscow, 1987, p.116 (In Russian).
30.R.P.Bazylevych, R.A.Melnyk. Macromodelling for Matrix LSI placement. Proc.Conf. "Avtomatizaciia konstruktorskoho proektirovania REA i EVA". Penza, 1986, pp.67-68 (In Russian).
31.R.P.Bazylevych, Yu.M.Hresko. Geometry route optimization for triangular routing area. Proc.Conf. "Mashinnye metody tekhnicheskoho proektirovania elekronno-vychislitelnoi apparatury.” Kaunas, 1983,pp.51-52 (In Russian).
32.R.P.Bazylevych, R.Pelke. Probleme der Optimierung der Leiter zugver legung bein Rechnergestiitzten Leiterplattenentwurf. 23 Intern.Wiss.Koll.TH Ilmenau, Vortragsreihe B5, Ilmenau, 1978, pp.117-120 (In German).
33.R.P.Bazylevych, M.I.Pavlykevych, Yu.M.Romanyshyn, R.Kharke. Microwave circuit analysis by the method of optimal rolling-up of subnetworks. Proc.6 Colloq. on Microwave Communication, Budapest, 1978, pp. II-1/4.1 - 1/4.4.
34.R.P.Bazylevych. Principles of algorithmic methods of flexible connection routing. IFAC-Workshop on computer control in discrete manufacturing, Prague, 1977, pp.19-23.
35.R.P.Bazylevych, E.F.Zamora, N.F.Storozenko, R.Pelke. Flexible Leiterzugverlegung fur Zweiseitige Leiterplatten mit Hilfe der EDVA'M-222'. XX Intern. Vissenschaftliches Kolloguium, Technishe Hochschule Ilmenau, Helf 3, 1975, pp.159-162 (In German).
36.R.P.Bazylevych, E.F.Zamora, M.I.Pavlykevych, I.I.Motyka. Computer-aided design of linear microwave circuits. Proc. 5 Colloq. on Microwave Communication. Budapest, 1974, pp.25-34.
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